 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| PLL620-88/-89 Low Phase Noise XO (9.5-65MHz Output) FEATURES * * * * * * 19MHz to 65MHz crystal input. Output range: 9.5MHz - 65MHz Complementary outputs: PECL or LVDS output. Selectable OE Logic (enable high or enable low). Supports 2.5V or 3.3V Power Supply. Available in 16 pin TSSOP package. PIN CONFIGURATION VDD XIN XOUT DNC S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DNC DNC GNDBUF QBAR VDDBUF Q GNDBUF GND PLL 620-8x DESCRIPTION The PLL620-88 (PECL) and PLL620-89 (LVDS) are XO ICs specifically designed to work with fundamental or 3 rd OT crystals between 19MHz and 65MHz. The selectable divide by two feature extends the operation range from 9.5MHz to 65MHz. They require very low current into the crystal resulting in better overall stability. The OE logic feature allows selection of enable high or enable low. OE N/C GND OUTPUT SELECTION AND ENABLE OE_SELECT OE_CTRL State 0 0 1 (Default) 0 (Default) 1 Tri-state Output enabled Output enabled Tri-state BLOCK DIAGRAM 1 (Default) O E Q Oscillator Amplifier S2 XQ Input selection: Bond to GND to set to "0", bond to VDD to set to "1" No connection results to "default" setting through internal pull-up/-down. OE_CTRL: Logical states defined by PECL levels if OE_SELECT is "1" Logical states defined by CMOS levels if OE_SELECT is "0" X+ OUTPUT FREQUENCY DIVIDE BY TWO SELECTOR PLL620-8X Block Diagram S2 Output 0 1 Intput/2 Input 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 1 PLL620-88/-89 Low Phase Noise XO (9.5-65MHz Output) PIN AND PAD ASSIGNMENT Name VDD XIN XOUT DNC S2 OE_CTRL DNC GND GNDBUF Q VDDBUF QBAR GNDBUF DNC DNC Pin# 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 Description Power Supply. Crystal input. See Crystal Specification on page 3. Crystal output. See Crystal Specification on page 3. Do Not Connect. Output Divide by Two selector pin. See the OUTPUT DIVIDE BY TWO SELECTOR Table on page 1. Output Enable input. See OUTPUT SELECTION AND ENABLE TABLE on page 1. Do Not Connect. Ground. Ground for output buffer circuitry. PECL or LVDS output. Power supply for output buffer circuitry. Complementary PECL or LVDS output. Ground for output buffer circuitry. Do Not Connect. Do Not Connect. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL VDD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. 4.6 VDD+0.5 VDD+0.5 150 85 125 260 2 UNITS V V V C C C C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 2 PLL620-88/-89 Low Phase Noise XO (9.5-65MHz Output) 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Recommended ESR SYMBOL FXIN CL (xtal) C0 RE CONDITIONS Fundamental MIN. 19 TYP. 8.5 MAX. 65 5 30 UNITS MHz pF pF AT cut 3. General Electrical Specifications PARAMETERS Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current SYMBOL IDD VDD CONDITIONS PECL/LVDS @ 1.25V (LVDS) @ VDD - 1.3V (PECL) MIN. TYP. MAX. 100/80 UNITS mA V % mA 2.97 45 45 50 50 50 3.63 55 55 4. Jitter Specifications PARAMETERS Period jitter RMS at 27MHz Period jitter peak-to-peak at 27MHz Accumulated jitter RMS at 27MHz Accumulated jitter peak-to-peak at 27MHz Random Jitter Measured on Wavecrest SIA 3000 CONDITIONS With capacitive decoupling between VDD and GND. Over 10,000 cycles With capacitive decoupling between VDD and GND. Over 1,000,000 cycles. "RJ" measured on Wavecrest SIA 3000 MIN. TYP. 2.3 18.5 2.3 24 2.3 MAX. 20 UNITS ps 25 ps ps 5. Phase Noise Specifications PARAMETERS Phase Noise relative to carrier FREQUENCY 27MHz @10Hz -75 @100Hz -100 @1kHz -125 @10kHz -140 @100kHz -145 UNITS dBc/Hz Note: Phase Noise measured on Agilent E5500 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 3 PLL620-88/-89 Low Phase Noise XO (9.5-65MHz Output) 6. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current SYMBOL VOD VOD VOH VOL VOS VOS IOXD IOSD CONDITIONS MIN. 247 -50 TYP. 355 1.4 MAX. 454 50 1.6 1.375 25 10 -8 UNITS mV mV V V V mV uA mA RL = 100 (see figure) 0.9 1.125 0 1.1 1.2 3 1 -5.7 Vout = VDD or GND VDD = 0V 7. LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time LVDS Levels Test Circuit OUT SYMBOL tr tf CONDITIONS RL = 100 CL = 10 pF (see figure) MIN. 0.2 0.2 TYP. 0.7 0.7 MAX. 1.0 1.0 UNITS ns ns LVDS Switching Test Circuit OUT CL = 10pF 50 VOD VOS VDIFF RL = 100 50 CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 20% 0V 80% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 4 PLL620-88/-89 Low Phase Noise XO (9.5-65MHz Output) 8. PECL Electrical Characteristics PARAMETERS Output High Voltage Output Low Voltage SYMBOL VOH VOL CONDITIONS RL = 50 to (VDD - 2V) (see figure) MIN. VDD - 1.025 MAX. VDD - 1.620 UNITS V V 9. PECL Switching Characteristics PARAMETERS Clock Rise Time Clock Fall Time SYMBOL tr tf PECL Levels Test Circuit CONDITIONS @20/80% - PECL @80/20% - PECL MIN. TYP. 0.6 0.5 MAX. 1.5 1.5 UNITS ns ns PECL Output Skew VDD OUT OUT 50 2.0V 50% 50 OUT OUT tSKEW PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 5 PLL620-88/-89 PACKAGE INFORMATION 16 PIN TSSOP ( mm ) Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H Low Phase Noise XO (9.5-65MHz Output) D A A1 e B C L ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PART NUMBER PLL620-8x PART NUMBER xC TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE O=TSSOP Order Number PLL620-88OC-R PLL620-88OC PLL620-89OC-R PLL620-89OC Marking P620-88 P620-88 P620-89 P620-89 OC OC OC OC Package Option TSSOP TSSOP TSSOP TSSOP - - - - Tape and Reel Tube Tape and Reel Tube PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 6 |
Price & Availability of PLL620-8XOC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |